1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to data processing systems having a first circuit driven by a first clock signal and a second circuit driven by a second clock signal, the first circuit and the second circuit together controlling the action of a third circuit.
2. Description of the Prior Art
It is known to provide a data processing system utilising more than one clock signal (e.g. a memory clock signal and an input/output clock signal) to control different circuits within the system. A situation which arises within such systems is that in which a first circuit driven by a first clock signal and a second circuit driven by a second clock signal co-operate to together control a third circuit. A typical circumstance of this would be the control of an input/output device, such as a disc controller, by the combined action of a bus controller operating at the bus clock speed and an input/output controller operating at the input/output clock speed. In this situation, the bus controller asserts an address upon the address bus and issues a request signal to the input/output controller to trigger the input/output controller to select the appropriate input/output device to perform the necessary operation. The input/output controller synchronizes the request signal to its own input/output clock signal and then issues the required control signals to the input/output device in synchronism with the input/output clock signal. When the required operation is completed, a grant signal is sent back to the bus controller, the grant signal first being synchronized back to the bus clock signal.
A constant aim within data processing systems is that their speed of operation should be as high as possible. Measures that increase the speed of operation are accordingly highly advantageous.